module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);
    parameter A = 3'd1,B = 3'd2,C = 3'd3,D = 3'd4,E = 3'd5,F = 3'd6;
    reg [6:0] next_state;
    always @(*)
        begin
            case(y)
                A:next_state = w?A:B;
                B:next_state = w?D:C;
                C:next_state = w?D:E;
                D:next_state = w?A:F;
                E:next_state = w?D:E;
                F:next_state = w?D:C;
                default:next_state = A;
            endcase
        end
    assign Y2 = ~w&y[A];
    assign Y4 = w&(y[B]|y[C]|y[E]|y[F]);
endmodule